89HPEB383 Datasheet, PDF (109/264 Pages) Integrated Device Technology – Topics discussed include the following

11. Power Management > Power States
95
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
L0 State
This is the normal operational mode.
L0s State
A low resume latency, energy-saving standby state. L0s support is required for ASPM. It is not
applicable to PCI-PM compatible power management.
L1 State
L1 is a high latency and low-power standby state. It is required for PCI-PM compatible power
management. The PEB383 does support L1 entry in ASPM. The L1 may be entered whenever the
bridge is programmed to a D3 state. L1 is also entered by ASPM when there is no pending packet to
transmit for 10us. TLP and DLLP communication over the link is prohibited when the PEB383 is in the
L1 state. L1 exit can be initiated by the PEB383 or an upstream device.
L2/L3 Ready
The L2/L3 Ready state is a staging point for the L2 or L3 states. The process is initiated after the PM
module software transitions the PEB383 into the D3 state and requests power management software to
initiate the removal of power and clocks. After the PCIe link enters the L2/L3 Ready state the PEB383
is ready for power removal. TLP and DLLP communication over link cannot occur while the PEB383
is in this state. It is also possible to remove power without first placing the PEB383 in the D3Hot state.
System software causes the root complex to broadcast the PME_Turn_Off message in preparation for
removing the main power source, and the PEB383 responds in order to complete entry into the L2/L3
Ready state.
L3 State
When the PEB383 is in L2/L3 Ready state, the removal of main power and clocks places the device
into the L3 state. The PEB383 does not support auxiliary power, therefore L2 power management state
is not supported.
LDn State
This is a PCIe link down pseudo state prior to L0.
Integrated Device Technology, Inc.
Confidential - NDA Required
PEB383 User Manual
July 25, 2011