89HPEB383 Datasheet, PDF (29/264 Pages) Integrated Device Technology – Topics discussed include the following

2. Signal Descriptions > PCI Interface Signals
15
2.3
PCI Interface Signals
Table 3: PCI Interface Signals
Name
PCI_AD[31:0]
PCI_CBEn[3:0]
PCI_CLK
PCI_CLKO[4:0]
PCI_DEVSELn
PCI_FRAMEn
Pin Type
PCI Bidir
PCI Bidir
PCI In
PCI Out
PCI Bidir
PCI Bidir
Description
Design Recommendation
Address/Data Bus. These multiplexed
signals provide a 32/64-bit address and
32-bit data bus.
None.
Command/Byte Enables. These
multiplexed signals indicate the current
transaction type.
None.
PCI Input Clock. This signal provides
timing for the PEB383, either from an
external clock or from one of the
PCI_CLKO[4:0] signals (see
“Clocking”).
None.
PCI Output Clocks
(see “Clocking”).
Point-to-point connection to PCI device.
IDT recommends a 33 Ohm series
termination resistor. In Master clocking
mode, PCI_CLKO[4] should be
connected to PCI_CLK.
Device Select. A target device asserts
this signal when it decodes its address
on the bus. The master samples the
signal at the beginning of a transaction,
and the target rescinds it at the end of
the transaction.
Pull up (8.2K) to VIO_PCI.
Frame. The current initiator drives this
signal to indicate the start and duration
of a transaction, and the bus target
samples it. The bus master rescinds the
signal at the end of the transaction.
Pull up (8.2K) to VIO_PCI.
Integrated Device Technology, Inc.
Confidential - NDA Required
PEB383 User Manual
July 25, 2011