89HPEB383 Datasheet, PDF (153/264 Pages) Integrated Device Technology – Topics discussed include the following

14. Register Descriptions > Register Map
139
14.3.13 PCI Bridge Control and Interrupt Register
Register name: PCI_MISC2
Reset value: 0x0000_00FF
Register offset: 0x03C
Bits
31:24
23:16
15:08
07:00
7
S_FPTP_
EN
6
5
Reserved
S_RESET MA_ERR
4
3
2
1
0
DISCARD DISCARD_ DISCARD2 DISCARD1
_SERR
STAT
VGA_
16BIT_EN
VGA_EN
ISA_EN
SERR_EN
S_
PERESP
INT_PIN
INT_LINE
Bits
31:28
27
26
Name
Description
Reserved
DISCARD_SERR
Reserved
Discard Timer SERR# Enable
This bit only applies in PCI mode. It enables the PEB383 to
generate either an ERR_NONFATAL (by default) or
ERR_FATAL transaction on the PCIe Interface when the
Secondary Discard Timer expires and a Delayed
Transaction is discarded from a queue in the bridge. The
severity is selectable only if Advanced Error Reporting is
supported.
0 = Do not generate ERR_NONFATAL or ERR_FATAL on
the PCIe Interface as a result of the expiration of the
Secondary Discard Timer. Note that an error message
can still be sent if Advanced Error Reporting is
supported and the Delayed Transaction Discard Timer
Expired Mask bit is clear.
1 = Generate ERR_NONFATAL or ERR_FATAL on the PCIe
Interface if the Secondary Discard Timer expires and a
Delayed Transaction is discarded from a queue in the
bridge.
DISCARD_STAT
Discard Timer Status
It is set to 1 when the Secondary Discard Timer expires and
a Delayed Completion is discarded from a queue in the
bridge.
0 = No discard timer error
1 = Discard timer error
Type
R
R/W
R/W1C
Reset value
0x0
0
0
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PEB383 User Manual
July 25, 2011