89HPEB383 Datasheet, PDF (123/264 Pages) Integrated Device Technology – Topics discussed include the following

109
13.
JTAG
Topics discussed include the following:
• “Overview”
• “TAP Controller Initialization”
• “Instruction Register”
• “Bypass Register”
• “JTAG Device ID Register”
• “JTAG Register Access”
• “Dedicated Test Pins”
• “Accessing SerDes TAP Controller”
13.1
Overview
The JTAG Interface is compliant with IEEE 1149.6 Boundary Scan Testing of Advanced Digital
Networks, as well as IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture
standards. There are five standard pins associated with the interface (JTAG_TMS, JTAG_TCK,
JTAG_TDI, JTAG_TDO, and JTAG_TRSTn) that allow full control of the internal TAP (Test Access
Port) controller.
The JTAG Interface has the following features:
• Contains a 5-pin Test Access Port (TAP) controller, with support for the following registers
— Instruction register (IR)
— Boundary scan register
— Bypass register
— Device ID register
— User test data register (DR)
• Supports debug access of the PEB383’s configuration registers
— During mission mode or not
— Bus arbitration with configuration cycles
• Supports the following instruction opcodes
— Sample/Preload
— Extest
— EXTEST_PULSE (1149.6)
— EXTEST_TRAIN (1149.6)
Integrated Device Technology, Inc.
Confidential - NDA Required
PEB383 User Manual
July 25, 2011