89HPEB383 Datasheet, PDF (101/264 Pages) Integrated Device Technology – Topics discussed include the following

87
10.
Reset and Clocking
Topics discussed include the following:
• “Reset”
• “Clocking”
10.1
Reset
The PEB383 inputs resets from upstream devices, and drives reset to downstream devices.
PCIE_PERSTn is the reset input to the bridge, and is normally connected to a power-on reset controller
at the system level. The PEB383 drives reset onto the PCI bus using PCI_RSTn (see Table 25).
Table 25: Reset Summary
Reset
Level
0
1
2
PCI Definition
Cold reset
Warm reset
Hot reset
PCI bus reset
Trigger
EEPROM
Load
PEB383 Actions
PCIE_PERSTn
Yes
• Initialize all registers to known state (including
sticky)
• Drive and release PCI_RSTn 1 ms after
PCIE_PERSTn is released
Reset message or
DL_down state
Yes
• Initialize all registers to known state (except
sticky
• Drive and release PCI_RSTn 1 ms after
PEB383 is completed reset
Set reset bit in CSR
No
• Hold PCI_RSTn low for 1 ms, or until bit is
through configuration
cleared by software, which ever is longer
cycle
• Drain traffic
• Drop request TLPs
• Enumerate bus mode and clock speed (if clock
master)
• Do not initialize CSR
Integrated Device Technology, Inc.
Confidential - NDA Required
PEB383 User Manual
July 25, 2011