89HPEB383 Datasheet, PDF (114/264 Pages) Integrated Device Technology – Topics discussed include the following

100
11. Power Management > Power Saving Modes
11.4
Power Saving Modes
The PEB383 provides several low power modes of operation, as described in Table 30.
Table 30: Power saving modes
Input Conditions
power saving activities
Mode state
ASPM^a
PCI_CLK[3:0]
gate enable^b
traffic
PCI_CLK[3:0] link state
internal
clock
1
DO
X
X
active
on
L0
on
2
DO
none
X
idle
on
L0
on
3
DO
L0s
X
idle
on
L0s
on
4
DO
L1
X
idle
on
L1
gated
5
D3_hot
X
no
idle
on
L1
gated
6
D3_hot
X
yes
idle
gated
L1
gated
a. ASPM enabled via “ASPM_CTL” bit of “PCIe Link Control Register”
b. PCI_CLK[3:0] gating enabled via “PCGE” bit “PCI Miscellaneous Clock Straps Register”
Mode1 is fully operational, no power saving modes used.
Mode2 has ASPM disabled, no power saving modes used.
Mode3 Has ASPM L0s enabled, link power is saved.
Mode4 has ASPM L1 enabled, additional link power is saved, and internal core logic clock is gated for
additional power savings
Mode5 is D3_hot, link is in L1, and internal clock is gated
Mode6 is D3_hot, link in L1, internal clock is gated, and external PCI_CLK[3:0] is gated.
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required