89HPEB383 Datasheet, PDF (144/264 Pages) Integrated Device Technology – Topics discussed include the following

130
14. Register Descriptions > Register Map
14.3.5
PCI Bus Number Register
Register name: PCI_BUSNUM
Reset value: Undefined
Register offset: 0x018
Bits
7
31:24
23:16
15:08
07:00
6
5
4
3
S_LTIMER
SUB_BUS_NUM
S_BUS_NUM
P_BUS_NUM
2
1
0
S_LTIMER_8
Bits
31:27
26:24
23:16
15:08
07:00
Name
Description
S_LTIMER
S_LTIMER_8
Secondary Latency Timer
This value is used by the PEB383 to perform burst transfers
on the PCI Interface. The lower 3 bits are hardwired to 0 so
that the timer is limited to 8-cycle granularity.
This field defines the minimum amount of time in PCI clock
cycles that the PEB383 can retain ownership as a bus
master on the PCI Interface.
00000 = PCI reset value
Set to 000 to force 8-cycle increments for the Secondary
Latency Timer.
SUB_BUS_NUM
Subordinate Bus Number
The system software programs this field with the PEB383’s
highest-numbered downstream secondary bus number. This
value is used by the PEB383 to respond to Type 1
Configuration transactions on the primary bus interface.
S_BUS_NUM
P_BUS_NUM[7:0]
Secondary Bus Number
The system software programs this field with the number of
the bridge’s immediate downstream secondary bus. This
value is used by the PEB383 to convert Type 1
Configuration transactions received on its primary bus
interface to Type 0 Configuration transactions.
Primary Bus Number
The system software writes to this field with the primary bus
number of the PEB383.
Type
R/W
R
R/W
R/W
R/W
Reset value
Undefined
000
0x00
0x00
0x00
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required