89HPEB383 Datasheet, PDF (216/264 Pages) Integrated Device Technology – Topics discussed include the following

202
14. Register Descriptions > Advanced Error Reporting Capability Registers
14.8.18 PCIe Secondary Header Log 3 Register
Register name: PCIE_SEC_HL3
Reset value: 0x0000_0000
Register offset: 0x144
Bits
7
6
5
4
3
2
31:24
23:16
TRAN_ADD[31:24]
TRAN_ADD[23:16]
15:08
07:00
TRAN_ADD[15:08]
TRAN_ADD[07:00]
Bits
31:00
Name
Description
TRAN_ADD[31:00]
Transaction Address
This is the first 32 bits of the 64-bit value transferred on
AD[31:0] during the first and second address phases.
The first address phase is logged in this field, and the
second address is logged in “PCIe Secondary Header Log 4
Register”.
1
Type
RS
0
Reset value
0x0
14.8.19 PCIe Secondary Header Log 4 Register
Register name: PCIE_SEC_HL4
Reset value: 0x0000_0000
Register offset: 0x148
Bits
7
6
5
4
3
2
31:24
TRAN_ADD[63:56]
23:16
15:08
TRAN_ADD[55:48]
TRAN_ADD[47:40]
07:00
TRAN_ADD[39:32]
Bits
31:00
Name
Description
TRAN_ADD[63:32]
Transaction Address
This is the second 32 bits of the 64-bit value transferred on
AD[31:0] during the first and second address phases.
The first address phase is logged in “PCIe Secondary
Header Log 3 Register”, and the second address phase is
logged in this field. In the case of a 32-bit address, this field
is set to 0.
1
Type
RS
0
Reset value
0x0
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required