89HPEB383 Datasheet, PDF (103/264 Pages) Integrated Device Technology – Topics discussed include the following

10. Reset and Clocking > Reset
89
10.1.1.3
10.1.2
Hot Reset – Level 1
A hot reset is triggered by an in-band message from the root complex over the PCIe link. After
application of hot reset, all registers are in their power-on reset state, except sticky bits which maintain
their pre-reset values in order to aid in system diagnostics.
A hot reset is also be initiated during a DL_down condition. DL_down means that the PEB383 has lost
communications at the physical or data link layer with the upstream device.
PCI Bus Reset
The PEB383 drives reset on the PCI bus using PCI_RSTn. There are four conditions that cause the
bridge to drive reset onto the PCI bus:
1. Assertion of PCIE_PERSTn (cold/warm reset)
2. Receipt of a hot reset message on the PCIe link (hot reset)
3. PCIe link going into a DL_down state (hot reset)
4. Setting the PCI bus reset bit, S_RESET, in the “PCI Bridge Control and Interrupt Register”
(level 2).
Software must ensure there are no requests pending in the device buffers before setting the PCI reset
bit. If software fails to do so, the PEB383 drains its buffers as follows.
• Drops all upstream requests and associated completions pending in the PCI Core buffers. Requests
pending in PCIe core buffers, however, are transmitted normally.
• Drops all downstream requests and returns the credits, and also returns completions with UR
completion status for non-posted requests.
Integrated Device Technology, Inc.
Confidential - NDA Required
PEB383 User Manual
July 25, 2011