IC42S16102 Datasheet, PDF (8/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

IC42S16102
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
Symbol Parameter
-5
-6
-7
Units
—
Clock Cycle Time
5
6
7
ns
—
Operating Frequency
200
166
143 MHz
tCAC CAS Latency
3
3
3
cycle
tRCD Active Command To Read/Write Command Delay Time
3
3
3
cycle
tRAC RAS Latency (tRCD + tCAC)
6
6
6
cycle
tRC
Command Period (REF to REF / ACT to ACT)
10
10
10
cycle
tRAS Command Period (ACT to PRE)
6
6
6
cycle
tRP
Command Period (PRE to ACT)
3
3
3
cycle
tRRD Command Period (ACT[0] to ACT [1])
2
2
2
cycle
tCCD Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
1
1
cycle
tDPL Input Data To Precharge Command Delay Time
2
2
2
cycle
tDAL Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
5
5
5
cycle
tRBD Burst Stop Command To Output in HIGH-Z Delay Time
3
3
3
cycle
(Read)
tWBD Burst Stop Command To Input in Invalid Delay Time
(Write)
0
0
0
cycle
tRQL Precharge Command To Output in HIGH-Z Delay Time
3
3
3
cycle
(Read)
tWDL Precharge Command To Input in Invalid Delay Time
(Write)
0
0
0
cycle
tPQL Last Output To Auto-Precharge Start Time (Read)
–2
–2
–2
cycle
tQMD DQM To Output Delay Time (Read)
2
2
2
cycle
tDMD DQM To Input Delay Time (Write)
0
0
0
cycle
tMCD Mode Register Set To Command Delay Time
2
2
2
cycle
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)
Input
CLK
2.4V
1.4V
0.4V
2.4V
INPUT 1.4V
0.4V
tCK
tCHI
tCL
tCS
tCH
tAC
tOH
OUTPUT
1.4V
1.4V
Output Load
ZO = 50Ω
I/O
50 Ω
50 pF
+1.4V
8
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005