IC42S16102 Datasheet, PDF (16/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

IC42S16102
OPERATION COMMAND TABLE^(1,2)
Current State Command
Operation
CS RAS CAS WE A11 A10 A9-A0
Write Recovery DESL
With Auto- NOP
Precharge BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Refresh
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Mode Register DESL
Set
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
No Operation, Idle State After tDAL Has Elapsed
No Operation, Idle State After tDAL Has Elapsed
No Operation, Idle State After tDAL Has Elapsed
Illegal⁽¹⁰⁾
Illegal⁽¹⁰⁾
Illegal⁽¹⁰⁾
Illegal⁽¹⁰⁾
Illegal
Illegal
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
No Operation, Idle State After tRP Has Elapsed
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
No Operation, Idle State After tMCD Has Elapsed
No Operation, Idle State After tMCD Has Elapsed
No Operation, Idle State After tMCD Has Elapsed
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
HXXXXXX
L HHHX X X
L HH L XXX
L
H
L
H
V
V
V⁽¹⁸⁾
L
H
L
L
V
V
V⁽¹⁸⁾
L
L
H
H
V
V
V⁽¹⁸⁾
L LHLVVX
L L LHXXX
LLLL
OP CODE
HXXXXXX
L HHHX X X
L HH L XXX
L
H
L
H
V
V
V⁽¹⁸⁾
L
H
L
L
V
V
V⁽¹⁸⁾
L
L
H
H
V
V
V⁽¹⁸⁾
L LHLVVX
L L LHXXX
LLLL
OP CODE
HXXXXXX
L HHHX X X
L HH L XXX
L
H
L
H
V
V
V⁽¹⁸⁾
L
H
L
L
V
V
V⁽¹⁸⁾
L
L
H
H
V
V
V⁽¹⁸⁾
L LHLVVX
L L LHXXX
LLLL
OP CODE
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input
2. All input signals are latched on the rising edge of the CLK signal.
3. Both banks must be placed in the inactive (idle) state in advance.
4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.
5. The row address is generated automatically internally at this time. The I/O pin and the address pin data is ignored.
6. During a self-refresh operation, all pin data (states) other than CKE is ignored.
7. The selected bank must be placed in the inactive (idle) state in advance.
8. The selected bank must be placed in the active state in advance.
9. This command is valid only when the burst length set to full page.
10. This is possible depending on the state of the bank selected by the A11 pin.
11. Time to switch internal busses is required.
12. The IS42S16102 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.
13. The IS42S16102 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.
14. Possible if tRRD is satisfied.
15. Illegal if tRAS is not satisfied.
16. The conditions for burst interruption must be observed. Also note that the IS42S16102 will enter the precharged state
immediately after the burst operation completes if auto-precharge is selected.
17. Command input becomes possible after the period tRCD has elapsed. Also note that the IS42S16102 will enter the
precharged state immediately after the burst operation completes if auto-precharge is selected.
18. A8,A9 = don't care.
16
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005