IC42S16102 Datasheet, PDF (33/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

IC42S16102
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IC42S16102 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IC42S16102 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continuing
with a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
must be executed with in the ACT to PRE command period
(tRAS max.) following the burst stop command. After the
period (tWBD) required for burst data input to stop following
the execution of the burst stop command has elapsed, the
write cycle terminates. This period (tWBD) is zero clock
cycles, regardless of the CAS latency.
CLK
COMMAND WRITE A0
I/O
DIN A0 DIN A1 DIN A
READ (CA=A, BANK 0)
CAS latency = 2, 3, burst length = full page
DIN A1 DIN A2
tWBD=0
tRP
BST
PRE 0
INVALID DATA
BURST STOP PRECHARGE (BANK 0)
Don’t Care
Burst Data Interruption Using the
U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (tQMD) after one of the U/
LDQM pins goes HIGH, the corresponding outputs go to
the HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
CLK
LOW, output is resumed at a time tQMD later. This output
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte output
(pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
COMMAND READ A0
UDQM
LDQM
tQMD=2
I/O8-I/O15
DOUT A0
DOUT A2 DOUT A3
HI-Z
HI-Z
I/O0-I/O 7
DOUT A0 DOUT A1
HI-Z
READ (CA=A, BANK 0) DATA MASK (LOWER BYTE)
CAS latency = 2, burst length = 4 ^{DATA MASK (UPPER BYTE)}
Integrated Circuit Solution Inc.
33
DR042-0A 01/18/2005