IC42S16102 Datasheet, PDF (7/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

IC42S16102
AC CHARACTERISTICS^(1,2,3)
Symbol Parameter
tCK3
Clock Cycle Time
tCK2
CAS Latency = 3
CAS Latency = 2
tAC3
Access Time From CLK⁽⁴⁾
tAC2
CAS Latency = 3
CAS Latency = 2
tCHI
CLK HIGH Level Width
tCL
CLK LOW Level Width
tOH
Output Data Hold Time
tLZ
Output LOW Impedance Time
tHZ3
Output HIGH Impedance Time⁽⁵⁾
tHZ2
CAS Latency = 3
CAS Latency = 2
tDS
Input Data Setup Time
tDH
Input Data Hold Time
tAS
Address Setup Time
tAH
Address Hold Time
tCKS
CKE Setup Time
tCKH
CKE Hold Time
tCKA
CKE to CLK Recovery Delay Time
tCS
Command Setup Time (CS, RAS, CAS, WE, DQM)
tCH
Command Hold Time (CS, RAS, CAS, WE, DQM)
tRC
Command Period (REF to REF / ACT to ACT)
tRAS
Command Period (ACT to PRE)
tRP
Command Period (PRE to ACT)
tRCD
Active Command To Read / Write Command Delay Time
tRRD
Command Period (ACT [0] to ACT[1])
tDPL
Input Data To Precharge
Command Delay time
tDAL
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
tTTransition Time
tREF
Refresh Cycle Time (4096)
-5
Min. Max.
5—
7—
— 4.5
—5
2—
2—
2—
0—
— 4.5
—5
2—
1—
2—
1—
2—
1—
1CLK+3 —
2—
1—
50 —
30 100,000
15 —
15 —
10 —
2CLK —
-6
Min. Max.
6—
8—
— 5.5
—6
2—
2—
2—
0—
— 5.5
—6
2—
1—
2—
1—
2—
1—
1CLK+3 —
2—
1—
60 —
36 100,000
18 —
18 —
12 —
2CLK —
-7
Min. Max Units
7 — ns
8.6 — ns
— 6 ns
— 6 ns
2.5 — ns
2.5 — ns
2 — ns
0 — ns
— 6 ns
— 6 ns
2 — ns
1 — ns
2 — ns
1 — ns
2 — ns
1 — ns
1CLK+3 — ns
2 — ns
1 — ns
70 — ns
42 100,000 ns
21 — ns
21 — ns
14 — ns
2CLK — ns
2CLK+tRP — 2CLK+tRP — 2CLK+tRP — ns
1 10
— 64
1 10
— 64
1 10 ns
— 64 ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated
voltages. Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and
VIL (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL
(max.) when the output is in the high impedance state.
Integrated Circuit Solution Inc.
7
DR042-0A 01/18/2005