IC42S16102 Datasheet, PDF (36/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

IC42S16102
OPERATION TIMING EXAMPLE
Power-On Sequence, Mode Register Set Cycle
T0
T1
T2
T3
T10
CLK
tCHI
tCK
tCL
CKE ^HIGH
tCS
tCH
CS
tCS
tCH
RAS
tCS
tCH
CAS
tCS
tCH
WE
A0-A9
A10
A11
tAS
tAH
BANK 0 & 1
DQM HIGH
I/O
WAIT TIME
T=100 s
tRP
tRC
<PALL>
<REF>
<REF>
CAS latency = 2, 3
T17
T18
T19
T20
tAS
tAH
CODE
tAS
tAH
CODE
tAS
tAH
CODE
ROW
ROW
BANK 1
BANK 0
tRC
tMCD
tRAS
tRC
<MRS>
<ACT>
Undefined
Don’t Care
36
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005