IC42S32400 Datasheet, PDF (53/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
Figure 18.3.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE ^High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
DQM
DQ ^Hi-Z
Activate
Command
Bank A
RBx
CAx
RBx
CBx
RBy
RBy
tRP
Ax Ax+1 Ax+2 _{Ax-2 Ax-1} Ax Ax+1 _{Bx Bx+1} Bx+2 Bx+3 Bx+4 Bx+5
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Full Page burst operation does not
Bank B ^{terminate when the burst length is}
Precharge
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
satisfied; the burst counter
increments and continues
bursting beginning with the
starting address.
Burst Stop
Command
Activate
Command
Bank B
Integrated Circuit Solution Inc.
53
DR038-0C 02/01/2005