IC42S32400 Datasheet, PDF (47/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
Figure 15.3.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RBw
A0-A9
RAx
CAx RBw
CBw
CBx
CBy
CAy
CBz
DQM
Hi-Z
DQ
tRCD
tRRD > tRRD(min)
tWR
tRP tWR(min)
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Integrated Circuit Solution Inc.
47
DR038-0C 02/01/2005