IC42S32400 Datasheet, PDF (27/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
Figure 4.Power on Sequene and Auto Refresh (CBR)
CLK
CKE
CS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High level
is required
Minimum of 2 Refresh Cycles are required
tMRS
RAS
CAS
WE
BS0, 1
A10
ADD
DQM
Hi-Z
DQ
High Level is Necessary
tRP
Precharge
Inputs ^Command
must ^{All Banks}
be stable
for 200us
1st Auto
Refresh
Command
Address Key
tRC
2nd Auto
Refresh
Command
Mode Register Command
Set Command
Integrated Circuit Solution Inc.
27
DR038-0C 02/01/2005