IC42S32400 Datasheet, PDF (29/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
Figure 6.2.Clock Suspension During Burst Read (Using CKE)
(Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
DQM
DQ Hi-Z
Ax0
Ax1
Ax2
tHZ
Ax3
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycle
Note:CKE to CLK disable/enable =1 clock
Clock Suspend
3 Cycle
Integrated Circuit Solution Inc.
29
DR038-0C 02/01/2005