IC42S32400 Datasheet, PDF (23/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
6.A.C.Test Conditions
LVTTL Interface
Reference Level of Output Signals
Output Load
Input Signal Levels
Transition Time (Rise and Fall)of Input Signals
Reference Level of Input Signals
Output
30pF
3.3V
1.2kΩ
870Ω
1.4V /1.4V
Reference to the Under Output Load (B)
2.4V /0.4V
1ns
1.4V
1.4V
Output
Z0=5 0 Ω
50Ω
30pF
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope
(1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns,(tR /2 -0.5)ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR &tF )=1 ns
If tR or tF is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously)when all input signals are held “NOP”state
and both CKE =”H”and DQM =”H.”The CLK signals must be started at the same
time.
2) After power-up,a pause of 200µ seconds minimum is required.Then,it is recom
mended that DQM is held “HIGH”(VDD levels)to ensure DQ output is in high
impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
Integrated Circuit Solution Inc.
23
DR038-0C 02/01/2005