IC42S32400 Datasheet, PDF (30/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
Figure 6.3.Clock Suspension During Burst Read (Using CKE)
(Burst Length=4,CAS#Latency=3)
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
DQM
DQ _Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Note:CKE to CLK disable/enable =1 clock
Ax0
Ax1
Ax2
tHZ
Ax3
Clock Suspend Clock Suspend
1 Cycle
2 Cycle
Clock Suspend
3 Cycle
30
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005