IC42S32400 Datasheet, PDF (42/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
Figure 13.2.Read and Write Cycle (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
CAx
CAy
DQM
Hi-Z
DQ
Ax0 Ax1 Ax2 Ax3
DAy0 DAy1
DAy3
Activate
Command
Bank A
Read
Command
Bank A
Write The Write Data
Command _{is Masked with a}
Bank A
Zero Clock
Latency
CAz
Az0 Az1
Az3
Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
Latency
42
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005