IC42S32400 Datasheet, PDF (17/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
• Burst Type Field (A3)
The Burst Type can be one of two modes,Interleave Mode or Sequential Mode.
A3 Burst Type
0 Sequential
1 Interleave
—Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which is input to the
device.The internal column address is varied by the Burst Length as shown in the following table.When the value
of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective.
Data n
0 1 2 3 4 5 6 7 - 255 256 257 -
Column Address ^{n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -}
2 words:
Burst Length
4 words:
8 words:
Full Page: Column address is repeated until terminated.
• Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address
bits in the sequence shown in the following table.
Data n
Column Address
Burst Length
Data 0 A7
A6
A5
A4
A3
A2
A1
A0
Data 1 A7
A6
A5
A4
A3
A2
A1
A0# 4 words
Data 2 A7
A6
A5
A4
A3
A2
A1# A0
Data 3 A7
A6
A5
A4
A3
A2
A1# A0#
8 words
Data 4 A7
A6
A5
A4
A3
A2# A1
A0
Data 5 A7
A6
A5
A4
A3
A2# A1
A0#
Data 6 A7
A6
A5
A4
A3
A2# A1# A0
Data 7 A7
A6
A5
A4
A3
A2# A1# A0#
• CAS#Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data.The minimum whole value of CAS#Latency depends on the frequency of CLK.The
minimum whole value satisfying the following formula must be programmed into this field.
tCAC(min)<=CAS#Latency X tCK
A6 A5 A4
00 0
00 1
01 0
01 1
1X
X
CAS#Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
Integrated Circuit Solution Inc.
17
DR038-0C 02/01/2005