IC42S32400 Datasheet, PDF (44/62 Pages) Integrated Circuit Solution Inc – 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM

IC42S32400
IC42S32400L
Figure 14.2.Interleaving Column Read Cycle (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ^T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
RAx
RAx
RAx
CAy
RAx
CBw
CBx
CBy
CAy
CBz
tRCD
tAC2
DQ ^Hi-Z
Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 _By0 By1 Ay0 _Ay1 Bz0 _Bz1 Bz2 Bz3
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
44
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005