GMS81508A Datasheet, PDF (47/91 Pages) Hynix Semiconductor – USERS MANUAL

HYUNDAI MicroElectronics
2.12.6. Multiple Interrupt
When an interrupt is accepted, and program flow goes to the interrupt service routine. The interrupt
master enable flag(I-flag) is automatically cleared and other interrupts are inhibited. When interrupt
service is completed by RETI instruction, I-flag is set automatically. If other interrupts are generated
during interrupt service, The interrupt having higher priority is accepted when the previous interrupt
service routine is completed.
In order to multiple interrupts, I-flag must be cleared by EI instruction within the interrupt routine.
Then, The higher priority interrupt is accepted among the interrupts that interrupt request flag is "1".

Interrupt Mode Register ( IMOD)
if IM1,IM0 is selected as a "01", the interrupt selected by IP0~IP3 can be accepted and other
interrupts are not accepted. Using this register, we can change the interrupt priority order by s/w.




R/W R/W R/W R/W R/W R/W
IMOD
<00F3_H>
7
6
5
4
3
2
1
0


IM1 IM0 IP3
IP2
IP1
IP0
Interrupt Mode Definition
 ^{00 : Mode 0 (Priority by H/W)}
01 : Mode 1(Definition by IP3 IP0)
1- : Inhibit Interrupt
Interrupt Definition Selection
0001 : INT0
0010 : INT1
0011 : INT2
0100 : INT3
0101 : TIMER0
0110 : TIMER1
0111 : TIMER2
1000 : TIMER3
1001 : ADC
1010 : WDT
1011 : BIT
1100 : SIO
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