GMS81508A Datasheet, PDF (24/91 Pages) Hynix Semiconductor – USERS MANUAL

BASIC INTERVAL TIMER DATA REGISTER
BITR
<00D3_H>
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
GMS81508/16
B.I.T data
2.5. WATCH DOG TIMER
The Watch Dog Timer is a means of recovery from a system problem.
In this Device, the Watch Dog Timer consists of 6-bit binary counter, 6-bit comparator and watch
dog timer register(WDTR). The source clock of WDT is overflow of Basic Interval Timer. The
interrupt request of WDT is generated when the counting value of WDT equal to the contents of
WDTR( bit0~5). This can be used as s/w interrupt or MICOM RESET signal(Watch Dog Function).
2.5.1. Control of Watch Dog Timer
It can be used as 6-bit timer or WDT according to bit5(WDTON) of Clock Control Register
(CKCTLR). The counter can be cleared by setting WDTCL ( Bit 6 of WDTR) and the WDTCL is
auto-cleared after 1 machine cycle. The initial state (after Reset) of WDTCL is “0”.

CLOCK CONTROL REGISTER
CKCTLR
<00D3_H>
W
W
W
W
W
W
7
6
5
4
3
2
1
0

 ^{WDTON ENPCK} BTCL BTS2 BTS1 BTS0
WDT ON
0 : 6-bit Timer
1 : Watch Dog Timer

WATCH DOG TIMER REGISTER
WDTR
<00E0_H>
W
W
W
W
W
W
W
W
7
6
5
4
3
2
1
0

WDTCL ^WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0
Watch Dog Timer Clear
0 : free run
1 : W.D.T counter clear
Determines the interval of W.D.T Interrupt
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