GMS81508A Datasheet, PDF (29/91 Pages) Hynix Semiconductor – USERS MANUAL

HYUNDAI MicroElectronics
By read Timer Data Register(TDR0~3),The counting value of timer can be read at any time.
2.6.2. Interval Timer
The interrupt cycle is determined by the source clock of timer and the contents of TDR.

Interrupt cycle = source clock the contents of TDR
In order to write data to TDR, you have to stop timer. otherwise, TDR value is invalid.
 Maximum Interrupt Cycle according to source clock
@ fex=8MHz
8-bit TIMER Mode
16-bit TIMER Mode
T0,T2
T1,T3
source clock
 PS2 ( 0.5 )
 PS4 ( 2 )
 PS6 ( 8 )
 PS2 ( 0.5 )
 PS4 ( 2 )
 PS6 ( 8 )
max. count
 128
 512
 2,048
 128
 512
 2,048
source clock
 PS2 ( 0.5 )
 PS4 ( 2 )
 PS6 ( 8 )
max. count
 32,768
 131,072
 524,288
2.6.3. Event Counter
The event counter operates in the same way as the interval timer except it counts the external
event input from R44/EC0 and R45/EC1 port. it only counts at the falling edge of event input clock.
In order to input of external event clock, the relevant Port Mode Register(bit4,bit5 of PMR4) is set
to "1". TDR value should be initialized to “FFH” because timer is cleared when it equals to TDR
value, but if you want to use interrupt, TDR value should be written to "1H~FFH".
2.6.4. Pulse Output
A pulse width 50% cycle duty is output to the R46/T1 O or R47/T3 O port and reverse the output
when timer interrupt is generated. This creates a pulse period which is two times that of the timer
interrupt cycle. The output pulse period is determined by the source clock of timer and the contents
of TDR.
   output period = source clock( ) the contents of TDR 2
In order to output of pulse, the bit6,bit7 of PMR4 is set to "1".
2.6.5. Input Capture
This function measures the period or width of pulse input from external INT. (R40/INT0, R42/INT2)
port. The period of pulse is measured by selecting rising edge or falling edge of the interrupt edge
select register(IEDS) and the width of pulse is measured by selecting both edge of IEDS.
The external interrupt is generated at the valid edge according to IEDS. At this time, The counting
value of timer is loaded into TDR and counter is cleared and restarts count-up.
24