GMS81508A Datasheet, PDF (44/91 Pages) Hynix Semiconductor – USERS MANUAL

GMS81508/16
IENH
<00F6_H>
IENL
<00F4_H>
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
INT0E INT1E INT2E INT3E T0E T1E T2E T3E
R/W R/W R/W R/W
-
-
-
-
7
6
5
4
3
2
1
0
AE WDTE BITE SE
-
-
-
-
Interrupt Masking Flag
0 : Interrupt Disable
1 : Interrupt Enable

Interrupt Request Flag Register ( IRQH, IRQL)
Whenever interrupt request is generated, the interrupt request flag is set. The request flag
maintains '1" until interrupt is accepted. The accepted interrupt request flag is automatically cleared
by interrupt process cycle. Interrupt Request Flag Register ( IRQH, IRQL) is Read/ Write Register.
So, it is possible to be checked and changed by program.
IRQH
<00F7_H>
IRQL
<00F5_H>
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
INT0R INT1R INT2R INT3R T0R T1R T2R T3R
R/W R/W R/W R/W
-
-
-
-
7
6
5
4
3
2
1
0
AR WDTR BITR SR
-
-
-
-
Interrupt Request Flag
0 : Disable
1 : Enable
2.12.3. Interrupt Priority
When two or more interrupts requests are generated at the same sampling point, the interrupt
having the higher priority is accepted. The interrupt priority is determined by H/W. however,
multiple priority processing through software is possible by using interrupt control flags(IENH, IENL,
I-flag) and interrupt mode register(IMOD).
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