GMS81508A Datasheet, PDF (23/91 Pages) Hynix Semiconductor – USERS MANUAL

HYUNDAI MicroElectronics
2.4. BASIC INTERVAL TIMER
The Basic Interval Timer(B.I.T.) has 8-bit binary counter. The operations is shown below.
. Generates reference time interval interrupt request as a timer.
. The counting value of B.I.T. can be read.
( Note; The writing at same address overwrites the CKCTLR.)
. The overflow of B.I.T be used the source clock of Watch Dog Timer.
Internal Data Bus
CKCTLR

 ^{WDTON ENPCK} BTCL BTS2 BTS1 BTS0
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
MUX
BITR
Same address
when read, it can be read as
counter value. When write, it can
be write as control register.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
IFBIT
Internal Data Bus
2.4.1. Control of Basic Interval Timer
The Basic Interval Timer is free running timer. When the counting value is changed "0FFH" to
"00H" , The interrupt request flag is generated. The counter can be cleared by setting BTCL (Bit 3
of CKCTLR) and the BTCL is auto-cleared after 1 machine cycle. The initial state (after Reset) of
BTCL is “0”.
The input clock of Basic Interval Timer is selected by BTS2~BTS0 (Bit2~0 of CKCTLR) among the
prescaler outputs (PS4~PS11).
The Basic Interval Timer Register (BITR) can be read.
The CKCTLR and the BITR have a same address (00D3H). So, If you write to this address, the
CKCTLR would be controlled. If you read this address, the counting value of BITR would be read.

CLOCK CONTROL REGISTER
CKCTLR
<00D3_H>
W
W
W
W
W
W
7
6
5
4
3
2
1
0

 ^{WDTON ENPCK} BTCL BTS2 BTS1 BTS0
B.I.T. input clock selection
B.I.T. CLEAR ( When writing )
0 : B.I.T. Free-run
1 : B.I.T. Clear ( auto cleared after 1 machine cycle )
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