GMS81508A Datasheet, PDF (25/91 Pages) Hynix Semiconductor – USERS MANUAL

HYUNDAI MicroElectronics
The interval of WDT interrupt is decided by the interrupt interval of Basic Interval Timer and the
contents of WDTR.

The interval of WDT = The contents of WDTR The interval of B.I.T.
Caution) Do not use the contents of WDTR = "0"
 The relationship between the input clock of B.I.T and the output of W.D.T. (@8MHz)
BTS2 BTS1 BTS0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
B.I.T. Input Clock
 PS4 ( 2 )
 PS5 ( 4 )
 PS6 ( 8 )
 PS7 ( 16 )
 PS8 ( 32 )
 PS9 ( 64 )
 PS10 ( 128 )
 PS11 ( 256 )
The cycle of B.I.T.
 512
 1,024
 2,048
 4,096
 8,192
 16,384
 32,768
 65,536
The cycle of W.D.T.(max)
 32,256
 64,512
 129,024
 258,048
 516,096
 1,032,192
 2,064,384
 4,128,768
2.5.2. The output of WDT signal
The overflow of WDT can be output through R54/WDT O port by setting bit4 of PMR5(WDTS) to
"1".

PORT R5 MODE REGISTER
PMR5
<00D1_H>
W
W
7
6
5
4
3
2
1
0
-
- BUZS WDTS -
-
-
-
R54/WDT O Selection
0 : R54 ( Input / Output )
1 : WDTO ( Output )
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