GMS81508A Datasheet, PDF (36/91 Pages) Hynix Semiconductor – USERS MANUAL

GMS81508/16
2.9.1. Data Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 SIOM) to ”1”. After one cycle of SCK,
SIOST is cleared automatically to “0”. The serial output data from 8-bit shift register is output at
falling edge of Sclk. and input data is latched at rising edge of Sclk. When transmission clock is
counted 8 times, serial I/O counter is cleared as “0”. Transmission clock is halted in “H” state
and serial I/O interrupt (IFSIO) occurred.
Input Clock
Sclk
SIOST
Sout
Sin
Output
D0
D1
D2
D3
D4
D5
D6
D7
Latch
D0
D1
D2
D3
D4
D5
D6
D7
IFSIO
Timing Diagram of Serial I/O
2.9.2. The Serial I/O operation by Srdy pin

transmission clock = external clock
The Srdy pin becomes "L" by SIOST = "1". This signal tells to the external system that this device
is ready for serial transmission. The external system detects the "L" signal and starts transmission.
The Srdy pin becomes "H" at the first rising edge of transmission clock.
SIOST
Srdy(Output)

transmission clock = internal clock
The I/O of Srdy pin is input mode. When the external system is ready to for serial transmission, the
"L" level is inputted at this pin. At this time this device starts serial transmission.
SIOST
Srdy(Input)
31