GMS77C1001 Datasheet, PDF (44/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
18. POWER FAIL DETECTION PROCESSOR
GMS77C1000X has an on-chip power fail detection cir-
cuitry to immunize against power noise.
If V_DD falls below a level for longer 100ns, the power fail
detection processor may reset MCU and preserve the de-
vice from the malfunction due to Power Noise.
OPTION
Register
LOWOPT PFDEN T0CS
T0SE
PSA
PS2
PS1
bit7
6
5
4
3
2
1
bit 7
LOWOPT: Power-fail detection level select bit.
1 = Lowered detection level (typ. 2.5V @ 5V)
0 = Normal detection level (typ. 3V @ 5V)
bit 6
PFDEN: Power-fail detection enable bit
1 = Enable power-fail detection
0 = Disable power-fail detection
PS0
bit0
FIGURE 18-1 POWER FAIL DETECTION PROCESSOR
The bit6(PFDEN) of OPTION register activates the PFD
Circuit, and bit7(LOWopt) lowers the detection level of
the Power Noise. The normal detection level is typically
3V and the lowered detection level is typically 2.5V. Fig-
ure 18-2 shows a Power Fail Detection Situations where
the detection level is selected by LOWOPT Bit.
Note: The PFD circuit is not implemented on the in circuit
emulator, user can not experiment with it. There
fore, after final development user program, this
function may be experimented on OTP
PFDEN = 1
LOWOPT = 0
V_DD
PFDR
Internal
RESET
V_DD
PFDEN = 1
LOWOPT = 1
PFDR
Internal
RESET
V_DD
T_NVDD ≥ 100nS
T_IRT
T_NVDD ≥ 100nS
T_IRT
V_DD ≤ V_DR
PFDEN = 1
LOWOPT = 0/1
T_IRT
PFDR
Internal
RESET
POR
When VDD falls below approximately 1V level, Power-On Reset may occur.
FIGURE 18-2 POWER FAIL DETECTION SITUATIONS
V_DD=3V
V_DR
V_DD=2.5V
V_DR
V_DD=3/(2.5)V
V_DR
July. 2001 Ver. 1.1
41