GMS77C1001 Datasheet, PDF (35/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
14. RESET
GMS77C100X devices may be reset in one of the follow-
ing ways:
- Power-On Reset (POR)
- Power-Fail detect reset (PFDR)
- RESET (normal operation)
- RESET wake-up reset (from SLEEP)
- WDT reset (normal operation)
- WDT wake-up reset (from SLEEP)
Each one of these reset conditions causes the program
counter to branch to reset vector address. (GMS77C1000
is 1FF_H and GMS77C1001 is 3FF_H ).
Table 14-1 shows these reset conditions for the PCL and
STATUS registers.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset state”
on Power-On Reset (POR), PFDR, RESET or WDT reset.
A RESET or WDT wake-up from SLEEP also results in a
device reset, and not a continuation of operation before
SLEEP.
The TO and PD bits (STATUS <4:3>) are set or cleared
depending on the different reset conditions. These bits may
be used to determine the nature of the reset.
Table 14-2 lists a full description of reset states of all reg-
isters. Figure 14-1 shows a simplified block diagram of the
on-chip reset circuit.
Condition
Power-On Reset
RESET reset or PFD
reset (normal operation)
RESET wake-up or PFD
reset (from SLEEP)
WDT reset (normal
operation)
WDT wake-up (from
SLEEP)
PCL
Addr: 02_H
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
STATUS
Addr: 03_H
0001 1xxx
000u uuuu¹
0001 0uuu
0000 uuuu²
0000 0uuu
TABLE 14-1 RESET CONDITIONS FOR SPECIAL
REGISTERS
1. TO and PD bits retain their last value until one of the other
reset conditions occur.
2. The CLRWDT instruction will set the TO and PD bits.
Legend : x = unknown, u = unchanged.
Register
Address
W
TRIS
OPTION
INDF
TMR0
PCL¹
STATUS¹
FSR
PORTA
PORTB
General Purpose Register Files
N/A
N/A
N/A
00_H
01_H
02_H
03_H
04_H
05_H
06_H
07-1F_H
Power-On
Reset
xxxx xxxx
1111 1111
0011 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
1xxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
TABLE 14-2 RESET CONDITIONS FOR ALL REGISTERS
1. See Table 14-1 for reset value for specific conditions.
Legend : - = unimplemented, read as ‘0’, x = unknown, u = unchanged.
q = see the tables in Section 17 for possible values.
Wake-up
Reset
uuuu uuuu
1111 1111
0011 1111
uuuu uuuu
uuuu uuuu
1111 1111
100q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
RESET, PFDR,
WDT Reset
uuuu uuuu
1111 1111
0011 1111
uuuu uuuu
uuuu uuuu
1111 1111
000q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
32
July. 2001 Ver. 1.1