GMS77C1001 Datasheet, PDF (36/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
V_DD
RESET/V_PP pin
Power-On
RESET
Power-Fail
Detect
Noise
Filter
WDT Time-Overflow
WDT
On-Chip
RC OSC
reset
clear
Internal RESET
Timer ( 8-bit asyn.
ripple counter )
SQ
RQ
Internal RESET
FIGURE 14-1 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
14.1 Power-On Reset (POR)
The GMS77C100X family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature, the
user merely ties the RESET/V_PP pin to VDD. A simplified
block diagram of the on-chip Power-On Reset circuit is
shown in Figure 14-1.
The Power-On Reset circuit and the Internal Reset Timer
circuit are closely related. On power-up, the reset latch is
set and the IRT is reset. The IRT timer begins counting
once it detects RESET to be high. After the time-out peri-
od, which is typically 7 ms (oscillation stabilization time),
it will reset the reset latch and thus end the on-chip reset
signal.
V_DD
RESET
T_IRT
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
FIGURE 14-2 TIME-OUT SEQUENCE ON POWER-UP (RESET NOT TIED TO V_DD)
July. 2001 Ver. 1.1
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