GMS77C1001 Datasheet, PDF (26/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
10. I/O PORTS
The GMS77C1000/1001 has a 4-bit I/O port(RA) and a 8-
bit I/O port(RB).
All pin have data(RA,RB) and direction(TRISA,TRISB)
registers which can assign these ports as output or input.
A “0” in the port direction registers configure the corre-
sponding port pin as output. Conversely, write “1” to the
corresponding bit to specify it as input pin (Hi-Z state).
For example, to use the even numbered bit of RB as output
ports and the odd numbered bits as input ports, write “55_H”
to TRISB register during initial setting as shown in Figure
10-1.
All the port direction registers in the GMS77C1000/1001
have “1” written to them by reset function. This causes all
port as input.
Write “55_H” to port RB direction register
76543210
TRISB 0 1 0 1 0 1 0 1
PORT RB ^{O U T IN O U T IN O U T IN O U T IN}
FIGURE 10-1 EXAMPLE OF PORT I/O ASSIGNMENT
10.1 Port RA
RA is a 4-bit I/O register. Each I/O pin can independently
used as an input or an output through the port direction reg-
ister, TRISA. A “0” in the TRISA register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.
Bits 7-4 are unimplemented and read as '0's.
RA Data Register
ADDRESS : 05_H
3 2 1 0 ^{RESET VALUE : Undefined}
RA R A 3 R A 2 R A1 R A 0
RA Direction Register
TRISA
ADDRESS : N/A
RESET VALUE : 0F_H
FIGURE 10-2 RA PORT REGISTERS
10.2 Port RB
RB is an 8-bit I/O register. Each I/O pin can independently
used as an input or an output through the port direction reg-
ister, TRISB. A “0” in the TRISB register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.
RB Data Register
765
ADDRESS : 06_H
RESET VALUE : Undefined
43210
RB R B 7 R B 6 R B5 R B 4 R B 3 R B2 R B 1 R B 0
RB Direction Register
TRISB
ADDRESS : N/A
RESET VALUE : FF_H
FIGURE 10-3 RB PORT REGISTERS
Note: A read of the ports reads the pins, not the output
data latches. That is, if an output driver on a pin is
enabled and driven high, but the external system is
holding it low, a read of the port will indicate that the
pin is low.
10.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in Fig-
ure 10-4. All ports may be used for both input and output
operation.
For input operations these ports are non-latching. Any in-
put must be present until read by an input instruction. The
outputs are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the corre-
sponding direction control bit (in TRISA, TRISB) must be
cleared (= 0). For use as an input, the corresponding TRIS
bit must be set. Any I/O pin can be programmed individu-
ally as input or output..
10.4 I/O Successive Operations
The actual write to an I/O port happens at the end of an in-
struction cycle, whereas for reading, the data must be valid
at the beginning of the instruction cycle (Figure 10-5).
Therefore, care must be exercised if a write followed by a
read operation is carried out on the same I/O port.
The sequence of instructions should allow the pin voltage
to stabilize (load dependent) before the next instruction,
which causes that file to be read into the CPU, is executed.
July. 2001 Ver. 1.1
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