GMS77C1001 Datasheet, PDF (22/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
9.3 Special Function Registers
This devices has seven special function register that are the
INDF register, the Program Counter(PC), the STATUS
register, File Select Register(FSR), 8-bit Timer(TMR0),
and I/O data register(RA, RB).
The Special Function Registers are registers used by the
CPU and peripheral functions to control the operation of
the device (Table 9-1).
TMR0, RA and RB are not in the G700 CPU. They are lo-
cated in each peripheral function blocks. All special func-
tion register are placed on data memory map. The INDF
register is not a physical register and this register is used
for indirect addressing mode...
Name
TRIS
OPTION
INDF
TMR0
PCL
STATUS
FSR
RA
RB
Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
N/A
I/O control registers (TRISA, TRISB)
N/A
Contains control bits to configure Timer0, Timer0/WDT
prescaler and PFD
00_H
Uses contents of FSR to address data memory (not a
physical register)
01_H
8-bit real-time clock/counter
02_H
Low order 8bits of PC
03_H
-
- PA0 TO PD Z DC C
04_H
Indirect data memory address pointer
05_H
-
-
-
- RA3 RA2 RA1 RA0
06_H
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
Power-On
Reset
1111 1111
0011 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
1xxx xxxx
---- xxxx
xxxx xxxx
RESET and
WDT Reset
1111 1111
0011 1111
uuuu uuuu
uuuu uuuu
1111 1111
000q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
TABLE 9-1 SPECIAL FUNCTION REGISTER SUMMARY
Legend : Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’
x = unknown, u = unchanged, q = see the tables in Section 17 for possible values.
9.3.1 INDF Register
The INDF register is not physically implemented register,
used for indirect addressing mode. If the INDF register
are accessed, CPU goes to indirect addressing mode. Then
CPU accesses the Data memory which address is the con-
tents of FSR.
If the INDF register are accessed in indirect addressing
mode(I.e., FSR=00H), 00H will be loaded into data bus.
This time, note the arithmetic status bits of STATUS reg-
ister may be affected.
Direct Addressing
4 (opcode) 0
location
select ⁰⁰H
The FSR<4:0> bits are used to select data memory ad-
dresses 00_H to 1F_H.
Data 0FH
Memory _10H
GMS77C1000 and GMS77C1001 do not use banking.
FSR<7:5> are unimplemented and read as '1's.
Indirect Addressing
4 ^(FSR) 0
location
select
1F_H
FIGURE 9-4 DIRECT/INDIRECT ADDRESSING
July. 2001 Ver. 1.1
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