GMS77C1001 Datasheet, PDF (43/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
17. TIME-OUT SEQUENCE AND POWER DOWN STATUS BITS (TO/PD)
The TO and PD bits in the STATUS register can be tested
to determine if a RESET condition has been caused by a
power-up condition, a RESET or Watchdog Timer (WDT)
reset, or a RESET or WDT wake-up reset.
TO PD
RESET was caused by
1 1 Power-up(POR)
u
u RESET or PFD reset (normal operation)¹
1
0
RESET Wake-up or PFD reset
(from SLEEP)
0 1 WDT reset (normal operation)
0 0 WDT wake-up reset (from SLEEP)
TABLE 17-1 TO/PD STATUS AFTER RESET
1. The TO and PD bits maintain their status (u) until a reset
occurs. A low-pulse on the RESET input does not change the
TO and PD status bits.
These STATUS bits are only affected by events listed in
Table 17-2.
Event
TO PD
Remarks
Power-up
1
1
WDT Time-out
0
u No effect on PD
SLEEP instruction
1
0
CLRWDT instruction 1
1
TABLE 17-2 EVENTS AFFECTING TO/PD STATUS
BITS
Note: A WDT time-out will occur regardless of the status of
the TO bit. A SLEEP instruction will be executed,
regardless of the status of the PD bit.
Table 14-1 lists the reset conditions for the special function
registers, while Table 14-2 lists the reset conditions for all
the registers.
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July. 2001 Ver. 1.1