GMS77C1001 Datasheet, PDF (41/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
16.2 Wake-up From SLEEP
The device can wake up from SLEEP through one of the
following events:
1. An external reset input on RESET pin.
2. A Watchdog Timer time-out reset (if WDT was en-
abled).
3. PFD reset
Both of these events cause a device reset. The TO and PD
bits can be used to determine the cause of device reset. The
TO bit is cleared if a WDT time-out occurred (and caused
wake-up). The PD bit, which is set on power-up, is cleared
when SLEEP is invoked.
The WDT is cleared when the device wakes from sleep, re-
gardless of the wake-up source.
16.3 Minimizing Current Consumption
The SLEEP mode is designed to reduce power consump-
tion. To minimize current drawn during SLEEP mode, the
user should turn-off output drivers that are sourcing or
sinking current, if it is practical.
It should be set properly that current flow through port
doesn't exist.
First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn’t
flow.
But input voltage level should be V_SS or V_DD. Be careful
that if unspecified voltage, i.e. if uncertain voltage level
(not V_SSor V_DD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
Note: In the SLEEP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware
is lowered; however, the power dissipation associat-
ed with the pin interface (depending on the external
circuitry and program) is not directly determined by
the hardware operation of the SLEEP feature. This
point should be little current flows when the input
level is stable at the power voltage level (V_DD/V_SS);
however, when the input level becomes higher than
the power voltage level (by approximately 0.3V), a
current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal
into the high-impedance state, a current flow across
the ports input transistor, requiring it to fix the level
by pull-up or other means.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re-
sistor then it is set to output mode, i.e. to high, and if there
is external pull-down register, it is set to low.
INPUT PIN
V_DD
V_DD
internal
pull-up
i
GND
VDD
X
Weak pull-up current flows
V_DD
O
OPEN
O
INPUT PIN
OPEN
i
V_DD
i=0
O
Very weak current flows
X
i=0
GND
O
When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.
FIGURE 16-3 APPLICATION EXAMPLE OF UNUSED INPUT PORT
38
July. 2001 Ver. 1.1