GMS77C1001 Datasheet, PDF (30/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
Name Address Bit7
Bit6
Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Power-On RESET and
Reset
WDT Reset
TMR0 01_H
8-bit real-time clock/counter
xxxx xxxx uuuu uuuu
OPTION N/A
LOWOPT PFDEN T0CS T0SE PSA PS2 PS1 PS0 0011 1111 0011 1111
TABLE 11-1 REGISTERS ASSOCIATED WITH TIMER0
Legend: x = unknown, u = unchanged.
11.3 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock requirement
is due to internal phase clock (T_OSC) synchronization. Al-
so, there is a delay in the actual incrementing of Timer0 af-
ter synchronization.
11.3.1 External Clock Synchronization
The synchronization of EC0 input with the internal phase
clocks is accomplished by sampling EC0 clock or the pres-
caler output on the Q2 and Q4 falling of the internal phase
clocks.
After the synchronization, counter increments on the next
instruction cycle (Q4). There is a small delay from the time
the external clock edge occurs to the time the Timer0 mod-
ule is actually incrementing. Figure 11-5 shows the syn-
chronization and the increment of the counter mode.
• EC0 clock specification
- No Prescaler (PSA = 0)
High or low time(min) ≥ 2T_XIN + 20ns
- With Prescaler (PSA = 1)
High or low time(min) ≥ 4T_XIN + 40ns
But, there is a noise filter on the EC0 pin, the minimum low
or high time(10ns) should be required.
11.3.2 Timer0 Increment Delay
Since the prescaler output is synchronized with the internal
clocks, there is a small delay from the time the external
clock edge occurs to the time the Timer0 module is actual-
ly incrementing. Figure 11-5 shows the delay from the ex-
ternal clock edge to the timer incrementing.
External Clock Input or
Prescaler Output⁽²⁾
External Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small Pulse
misses sampling
(1)
(3)
T0
T0+1
T0+2
Note 1: Delay from clock input change to TMR0 increment is 3T_XIN to 7T_XIN . (Duration of Q = T_XIN).
Therefore, the error in measuring the interval between two edges on TMR0 input = ±4T_XIN max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
FIGURE 11-5 TIMER0 TIMING WITH EXTERNAL CLOCK
11.4 Prescaler
The prescaler may be used by either the Timer0 module or
the Watchdog Timer, but not both. Thus, a prescaler as-
signment for the Timer0 module means that there is no
prescaler for the WDT, and vice-versa.
The prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is neither
readable nor writable.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio. When the prescal-
er is assigned to the Timer0 module, prescale values of 1:2,
July. 2001 Ver. 1.1
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