GMS77C1001 Datasheet, PDF (23/44 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS77C1000/GMS77C1001
9.3.2 TMR0 Register
The TMR0 register is a data register for 8-bit timer/
counter. In reset state, the TMR0 register is initialized with
“00_H”.
9.3.3 Program Counter (PC)
The program counter contains the 10-bit address of the in-
struction to be executed(9-bit address for GMS77C1000).
The lower 8 bits of the program counter are contained in
the PCL register which can be provided by the instruction
word for a call instruction, or any instruction where the
PCL is the destination while the ninth bit of the program
counter comes from the page address bit - PA0 of the STA-
TUS register(GMS77C1001 only).
This is necessary to cause program branches across pro-
gram memory page boundaries.
Prior to the execution of a branch operation, the user must
initialize the PA0 bit of STATUS register.
The eighth bit of the program counter can come from the
instruction word by execution of goto instruction, or can be
cleared by execution of call or any instruction where the
PCL is the destination.
In reset state, the program counter is initialized with
“1FF_H”(GMS77C1000) or “3FF_H”(GMS77C1001).
Note: Because PC<8> is cleared in the subroutine call in-
struction, or any Modify PCL instruction, all subrou-
tine calls or computed jumps are limited to the first
256 locations of any program memory page (512
words long).
jump instrunciton
8
0
PC
PCL
Instruction Word
subroutine call instruction
87
0
PC
PCL
Reset to ‘0’
Instruction Word
FIGURE 9-5 LOADING OF BRANCH INSTRUCTION -
GMS77C1000
jump instruction
98
0
PC
PCL
Instruction Word
PA0
subroutine call Instruction
9 87
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
FIGURE 9-6 LOADING OF BRANCH INSTRUCTION -
GMS77C1001
9.3.4 Stack Operation
The GMS77C1000/1001 have a 2-level hardware stack.
The stack register consists of two 9-bit save regis-
ters(GMS77C1000), 10-bit save registers(GMS77C1001).
A physical transfer of register contents from the program
counter to the stack or vice versa, and within the stack, oc-
curs on call and return instructions. If more than two se-
quential call instructions are executed, only the most recent
two return address are stored. If more than two sequential
return instructions are executed, the stack will be filled
with the address previously stored in level 2. The stack
cannot be read or written by program.
GMS77C1001(GMS77C1000)
9(8)
subroutine call
subroutine call
PC
STACK LEVEL1
STACK LEVEL2
0
return
return
FIGURE 9-7 OPERATION OF 2-LEVEL STACK
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July. 2001 Ver. 1.1