HYMP112F72CP8N3-C4 Datasheet, PDF (4/32 Pages) Hynix Semiconductor – 240pin Fully Buffered DDR2 SDRAM DIMMs

1240pin Fully Buffered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
Pin Name Pin Name Pin Name Pin
Name
Pin Name Pin
1
VDD
41
PN13
81
VSS
121
VDD
161
SN13
201
2
VDD
42
VSS
82
PS4
122
VDD
162
VSS
202
3
VDD
43
VSS
83
PS4
123
VDD
163
VSS
203
4
VSS
44
RFU*
84
VSS
124
VSS
164
RFU*
204
5
VDD
45
RFU*
85
VSS
125
VDD
165
RFU*
205
6
VDD
46
VSS
86
RFU*
126
VDD
166
VSS
206
7
VDD
47
VSS
87
RFU*
127
VDD
167
VSS
207
8
VSS
48
PN12
88
VSS
128
VSS
168
SN12
208
9
VCC
49
PN12
89
VSS
129
VCC
169
SN12
209
10
VCC
50
VSS
90
PS9
130
VCC
170
VSS
210
11
VSS
51
PN6
91
PS9
131
VSS
171
SN6
211
12
VTT
52
PN6
92
VSS
132
VCC
172
SN6
212
13
VCC
53
VSS
93
PS5
133
VCC
173
VSS
213
14
VSS
54
PN7
94
PS5
134
VSS
174
SN7
214
15
VTT
55
PN7
95
VSS
135
VTT
175
SN7
215
16
VID1
56
VSS
96
PS6
136
VID0
176
VSS
216
17 RESET 57
PN8
97
PS6
137 DNU/M_Test 177
SN8
217
18
VSS
58
PN8
98
VSS
138
VSS
178
SN8
218
19 RFU** 59
VSS
99
PS7
139
RFU**
179
VSS
219
20 RFU** 60
PN9
100
PS7
140
RFU**
180
SN9
220
21
VSS
61
PN9
101
VSS
141
VSS
181
SN9
221
22
PN0
62
VSS
102
PS8
142
SN0
182
VSS
222
23
PN0
63
PN10
103
PS8
143
SN0
183
SN10
223
24
VSS
64
PN10
104
VSS
144
VSS
184
SN10
224
25
PN1
65
VSS
105 RFU** 145
SN1
185
VSS
225
26
PN1
66
PN11
106 RFU**
146
SN1
186
SN11
226
27
VSS
67
PN11
107
VSS
147
VSS
187
SN11
227
28
PN2
68
VSS
108
VDD
148
SN2
188
VSS
228
29
PN2
Key
109
VDD
149
SN2
Key
229
30
VSS
69
VSS
110
VSS
150
VSS
189
VSS
230
31
PN3
70
PS0
111
VDD
151
SN3
190
SS0
231
32
PN3
71
PS0
112
VDD
152
SN3
191
SS0
232
33
VSS
72
VSS
113
VDD
153
VSS
192
VSS
233
34
PN4
73
PS1
114
VSS
154
SN4
193
SS1
234
35
PN4
74
PS1
115
VDD
155
SN4
194
SS1
235
36
VSS
75
VSS
116
VDD
156
VSS
195
VSS
236
37
PN5
76
PS2
117
VTT
157
SN5
196
SS2
237
38
PN5
77
PS2
118
SA2
158
SN5
197
SS2
238
39
VSS
78
VSS
119
SDA
159
VSS
198
VSS
239
40
PN13
79
PS3
120
SCL
160
SN13
199
SS3
240
80
PS3
200
SS3
NC= No Connect, RFU= Reserved for Future Use.
Note:
*: These pin positions are reserved for forwarded clocks to be used in future module implementations
**: These pin positions are reserved for future architecture flexibility
1) The following signals are CRC bits and thus appear out of the normal sequence:
PN12/ PN12, SN12 / SN12, PN13 / PN13, SN13 / SN13,PS9 / PS9, SS9 / SS9
Name
VSS
SS4
SS4
VSS
VSS
RFU*
RFU*
VSS
VSS
SS9
SS9
VSS
SS5
SS5
VSS
SS6
SS6
VSS
SS7
SS7
VSS
SS8
SS8
VSS
RFU*
RFU*
VSS
SCK
SCK
VSS
VDD
VDD
VDD
VSS
VDD
VDD
VTT
VDDSPD
SA0
SA1
Rev 1.01 / Sep. 2008
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