HYMP112F72CP8N3-C4 Datasheet, PDF (25/32 Pages) Hynix Semiconductor – 240pin Fully Buffered DDR2 SDRAM DIMMs

1240pin Fully Buffered DDR2 SDRAM DIMMs
IDD Power Supply Currents Specifications.
SAC Timing Parameters by Speed Grade
Power Supply
Icc_Idle_0 @1.5V
Idd_Idle_0 @1.8V
Idle_0 Total Power
Icc_Idle_1 @1.5V
Idd_Idle_1 @1.8V
Idle_1 Total Power
Icc_Idle_2 @1.5V
Idd_Idle_2 @1.8V
Idle_2 Total Power
Icc_Active_1 @1.5V
Idd_Active_1 @1.8V
Active_1 Total Power
Icc_Active_2 @1.5V
Idd_Active_2 @1.8V
Active_2 Total Power
Icc_L0s @1.5V
Idd_L0s @1.8V
L0s Total Power
Icc_Training @1.5V
Idd_Training @1.8V
Training Total Power
Max.
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Note1)
Note:
1) Assure that Primary channel Drive strength at 100% with De-emphasis at -6.5dB Secondary channel drive strength
at 60% with De-emphasis at -3dB when enabled. Address and Data fields are pseudo-random, which provides a 50%
toggle rate on DRAM data lines and link lanes when data is being transferred.
Assuming 1 activate command and 1 read/write command per BL=4 transferBL=4.10 lanes southbound and 14 lanes
northbound are enabled and active (12 lanes NB if non-ECC DIMM).
SPD specific assumption:Number of devices on the specific DIMM assumed.Termination of command, address, and
control is actual value used on the DIMM. ECC or non-ECC as per the specific DIMM.
SPD specifies Delta TAMB power spec specific assumptions: Dual rank x8 ECC DIMM assumed (18 DRAM devices
present on DIMM)
Modeled with 27 ohm termination for command, address, and clocks, and 47 ohm termination for control.
ECC DIMM assumed (72 bit data, 14 lanes northbound). AMB specification specifies current for each rail.
Rev 1.01 / Sep. 2008
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