HYMP112F72CP8N3-C4 Datasheet, PDF (3/32 Pages) Hynix Semiconductor – 240pin Fully Buffered DDR2 SDRAM DIMMs

1240pin Fully Buffered DDR2 SDRAM DIMMs
Input/Output Functional Description
Pin Name
type
SCK
Input
SCK
Input
PN[13:0]
Output
PN[13:0]
Output
PS[9:0]
Input
PS[9:0]
Input
SN[13:0]
Output
SN[13:0]
Output
SS[9:0]
Input
SS[9:0]
Input
SCL
Input
SDA
Input / Output
SA[2:0]
Input
VID[1:0]
Input
RESET
RFU
VCC
VDD
VTT
VDDSPD
VSS
Input
-
Supply
Supply
Supply
Supply
Supply
DNU/M_Test - / Analog
Polarity
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
-
-
-
-
Active Low
-
+1.5V
+1.8V
+0.9V
+3.3V
- / 0.9V
Function Description
Count
System clock input
1
System clock input
1
Primary Northbound Data
14
Primary Northbound Data
14
Primary Southbound Data
10
Primary Southbound Data
10
Secondary Northbound Data
14
Secondary Northbound Data
14
Secondary Southbound Data
10
Secondary Southbound Data
10
Serial Presence Detect (SPD) Clock Input
1
SPD Data Input / Output
1
SPD Address inputs, also used to select the DIMM number in the AMB
3
Voltage ID: These pins must be unconnected for DDR2-based Fully buff- 2
ered DIMMs
AMB reset signal
1
Reserved for Future Use
16
AMB Core Power and AMB channel Interface Power(1.5volt)
8
DRAM Power and AMB DRAM I/O Power
24
DRAM Address/Command/Clock Termination Power(VDD/2)
4
SPD Power
1
Ground
80
The DNU/M_Test pin provides an external connection on R/Cs A-D for
1
testing the margin of Vref which is produced by a voltage divider on the
module. It is not intended to be used in normal system operation and
must not be connected(DNU) in a system. This test pin may have other
features on future card designs and if it does, will be included in this
specification at that time.
Total
240
Rev 1.01 / Sep. 2008
3