HYMP112F72CP8N3-C4 Datasheet, PDF (18/32 Pages) Hynix Semiconductor – 240pin Fully Buffered DDR2 SDRAM DIMMs

1240pin Fully Buffered DDR2 SDRAM DIMMs
3. Advanced Memory Buffer Block Diagram
10x2
South bound
Data in
10x2
South bound
Data out
1x2
Ref Clock
Reset#
SMbus
PLL
Demux
Re-Time
Re-synch
Data Merge
PISO
Reset
Control
I0*12
Link init SM &
Control & CSRs
I0*12
MUX
Init
patterns
Command
Decoder &
CRC Check
Thermal
Sensor
Core Control
& CSRs
Failover
36 Deep
Write
Data
FIFO
IBIST - RX
IBIST - RX
DRAM Cmd
LAI Logic
DDR State
Controller
& CSRs
External MEMBIST
DDR Calibration &
DDR IOBIST/DFX
LAI
Controller
SMbus
Controller
Data CRC Gen
& Read FIFO
MUX
Failover
Sync & Idle
Pattern Generator
NB LAI
Buffer
IBIST - TX IBISt - RX
Link init SM &
Control & CSRs
14*6*2
PISO
14*12
Demux
Data Merge
Re-synch
Re-Time
Cmd
Out
Data
Out
Data In
4
DRAMclock
4
DRAMclock#
DDR
IOss
29
DRAM Address
/CommandCopy1
29
DRAM Address
/CommandCopy2
72+18X2
DRAM Address
Data/Strobe
Northbound
DataOut
14x2
14x2
Northbound
DataIn
Advanced Memory Buffer Block Diagram
Rev 1.01 / Sep. 2008
18