HYMP112F72CP8N3-C4 Datasheet, PDF (13/32 Pages) Hynix Semiconductor – 240pin Fully Buffered DDR2 SDRAM DIMMs

1240pin Fully Buffered DDR2 SDRAM DIMMs
Advanced Memory Buffer Pin Description
Pin Name
SCL
SDA
SA{2:0]
PLLTSTO
VCCAPLL
VSSAPLL
TEST_pin#
TESTLO_pin#
BFUNC
RESET
NC
RFU
V_CC
V_CCFBD
V_DD
V_DDSPD
V_SS
Pin Description
SPD Bus Interface Signals
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
SPD Address Inputs, also used to select the DIMM number in the AMB
Miscellaneous Signals
PLL Clock Observability Output
Analog VCC for the PLL. Tied with low pass filter to VCC.
Analog VSS for the PLL. Tied to
Leave floating on the DIMM
Tie to ground on the DIMM²
Tie to ground to set functionality as “buffer on DIMM.”
AMB reset signal
No connect. Many NC are connected to VDD on the DIMM, to lower the
impedance of the VDD power islands.
Reserved for Future Use
Power/Ground Signals
AMB Core Power(1.5 Volt)
AMB Channel I/O Power(1.5 Volt)
AMB DRAM I/O Power (1.8 Volt)
SPD Power (3.3 Volt)
Ground
Total
Count
5
1
1
3
163
1
1
1
6
5
1
1
129
18
213
24
8
24
1
156
655
Note:
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/ CK frequency.
2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on protype DIMMs: each pin should
have a zero ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC.
These resistors can be replaced on production DIMMs with a direct connection to ground.
Rev 1.01 / Sep. 2008
13