HY29LV320 Datasheet, PDF (34/44 Pages) Hynix Semiconductor – 32 Mbit (2M x 16) Low Voltage Flash Memory

HY29LV320
AC CHARACTERISTICS
Program and Erase Operations
Parameter
JEDEC Std
Description
Speed Option
Unit
- 70 - 80 - 90 - 12
t_AVAV
t_AVWL
t_WLAX
t_WC Write Cycle Time ¹
t_AS Address Setup Time
t_AH Address Hold Time
t_AST
Address Setup Time to OE# or CE# Low for
Toggle Bit Test
Min 70 80 90 120 ns
Min
0
ns
Min 45 45 45 50 ns
Min
15
ns
t_AHT
Address Hold Time from OE# or CE# High for
Toggle Bit Test
Min
0
ns
t_DVWH
t_WHDX
t_GHWL
t_ELWL
t_WHEH
t_WLWH
t_WHWL
t_WHWH1
t_CEPH
t_OEPH
t_DS
t_DH
t_GHWL
t_CS
t_CH
t_WP
t_WPH
Chip Enable High Time for Toggle Bit Test
Output Enable High Time for Toggle Bit Test
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
CE# Setup Time
CE# Hold Time
Write Pulse Width
Write Pulse Width High
t_WHWH1 Word Programming Operation ^{1, 2, 3}
Min
20
ns
Min
20
ns
Min 45 45 45 50 ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min 35 35 35 50 ns
Min
30
ns
Typ
11
µs
Max
300
µs
Chip Programming Operation ^{1, 2, 3, 5}
Typ
23
sec
Max
70
sec
Typ
7
µs
t_WHWH1 t_WHWH1 Accelerated Word Programming Operation ^{1, 2, 3}
Max
210
µs
t_WHWH2 t_WHWH2 Sector Erase Operation ^{1, 2, 4}
Typ
0.5
sec
Max
7.5
sec
t_WHWH3 t_WHWH3 Chip Erase Operation ^{1, 2, 4}
Typ
32
sec
Erase and Program Cycle Endurance ¹
Min
100,000
cycles
Typ
1,000,000
cycles
t_VCS V_CC Setup Time ¹
Min
50
µs
t_VHH V_HH Rise and Fall Time ¹
Min
250
ns
t_RB Recovery Time from RY/BY#
Min
0
ns
t_BUSY WE# High to RY/BY# Delay
Min
90
ns
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, V_CC = 3.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-
tions of 90 °C, V_CC = 2.7 volts (3.0 volts for - 70 version), 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program
command. See Table 9 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
word program time specified is exceeded. See Write Operation Status section for additional information.
34
r1.3/May 02