HY29LV320 Datasheet, PDF (25/44 Pages) Hynix Semiconductor – 32 Mbit (2M x 16) Low Voltage Flash Memory

HY29LV320
Table 14. Write and Erase Operation Status Summary ¹
Mode
Operation
DQ[7] DQ[6] DQ[5] DQ[3] DQ[2] RY/BY#
Programming in progress
DQ[7]# Toggle
0/1 ²
N/A
N/A
0
Programming completed
Normal
Erase in progress
Data
Data ⁴
Data
Data
Data
1
0
Toggle
0/1 ²
1³
Toggle
0
Erase completed ⁵
Data
Data ⁴
Data
Data
Data ⁴
1
Read within erase suspended
sector
1 No toggle
0
N/A
Toggle
1
Erase ^{Read within non-erase}
Suspend ^{suspended sector}
Data
Data
Data
Data
Data
1
Programming in progress ⁶
DQ[7]# Toggle
0/1 ²
N/A
N/A
0
Programming completed ⁶
Data
Data ⁴
Data
Data
Data
1
Notes:
1. A valid address is required when reading status information (except RY/BY#). For a programming operation, the ad-
dress used for the read cycle should be the program address. For an erase operation, the address used for the read
cycle should be any address within a non-protected sector marked for erasure (any address within a non-protected
sector for the chip erase operation).
2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.
3. A ‘1’ during sector erase indicates that the 50 µs time-out has expired and active erasure is in progress. DQ[3] is not
applicable to the chip erase operation.
4. Equivalent to ‘No Toggle’ because data is obtained in this state.
5. Data (DQ[7:0]) = 0xFF immediately after erasure.
6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).
and ignores the command for the specified sec-
tors that are protected.
When the system detects that DQ[7] has changed
from the complement to true data (or “0” to “1” for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is as-
serted low.
Figure 9 illustrates the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Auto-
matic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be read
at any address, and is valid after the rising edge
of the final WE# pulse in the Program or Erase
command sequence, including during the sector
erase time-out. The system may use either OE#
or CE# to control the read cycles.
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode) cause
DQ[6] to toggle. DQ[6] stops toggling when the op-
eration is complete. If a program address falls within
a protected sector, DQ[6] toggles for approximately
1 µs after the program command sequence is writ-
ten, then returns to reading array data.
While the Automatic Erase algorithm is operating,
successive read cycles at any address cause
DQ[6] to toggle. DQ[6] stops toggling when the
erase operation is complete or when the device is
placed in the Erase Suspend mode. The host may
use DQ[2] to determine which sectors are erasing
or erase-suspended (see below). After an Erase
command sequence is written, if all sectors se-
lected for erasing are protected, DQ[6] toggles for
approximately 100 µs, then returns to reading ar-
ray data. If at least one selected sector is not
protected, the Automatic Erase algorithm erases
the unprotected sectors, and ignores the selected
sectors that are protected.
DQ[2] - Toggle Bit II
Toggle Bit II, DQ[2], when used with DQ[6], indi-
cates whether a particular sector is actively eras-
ing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
r1.3/May 02
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