HY29LV320 Datasheet, PDF (18/44 Pages) Hynix Semiconductor – 32 Mbit (2M x 16) Low Voltage Flash Memory

HY29LV320
status of the programming operation, as described
in the Write Operation Status section.
Commands written to the device during execution
of the Automatic Program algorithm are ignored.
Note that a hardware reset immediately terminates
the programming operation (see Reset Operation
Timings). To ensure data integrity, the user should
reinitiate the aborted Program Command se-
quence after the reset operation is complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
to a “1”. Attempting to do so will cause the
HY29LV320 to halt the operation and set DQ[5] to
“1”, or cause the Data# Polling algorithm to indi-
cate the operation was successful. However, a
succeeding read will show that the data is still “0”.
Figure 6 illustrates the programming operation.
Unlock Bypass Command Sequence
Unlock bypass provides a faster method than the
normal Program Command for the host system to
program the array. As shown in Table 9, the Un-
lock Bypass Command sequence consists of two
unlock write cycles followed by a third write cycle
containing the unlock bypass command, 0x20.
The device then enters Unlock Bypass mode. In
this mode, a two-cycle Unlock Bypass Program
Command sequence is used instead of the stan-
dard four-cycle sequence to invoke a program-
ming operation. The first cycle in this sequence
contains the unlock bypass program command,
0xA0, and the second cycle specifies the program
address and data, thus eliminating the initial two
unlock cycles required in the standard Program
Command sequence. Additional data is pro-
grammed in the same manner. The unlock by-
pass mode does not affect normal read operations.
During the unlock bypass mode, only the Unlock
Bypass Program and the Unlock Bypass Reset
commands are valid. To exit the Unlock Bypass
mode, the host must issue the two-cycle Unlock
Bypass Reset command sequence shown in Table
9.
Figure 6 illustrates the procedures for the normal
and unlock bypass program operations.
The device automatically enters the unlock bypass
mode when it is placed in Accelerate mode via
the ACC pin.
START
NO
Enable Fast
Programming?
YES
Issue UNLOCK BYPASS
Command
Setup Next Address/Data for
Program Operation
NO
Unlock Bypass
Mode?
Issue NORMAL PROGRAM
Command
YES
Issue UNLOCK BYPASS
PROGRAM Command
Check Programming Status DQ[5] Error Exit
(See Write Operation Status
Section)
Programming Verified
NO
Last Word/Byte
Done?
YES
NO
Unlock Bypass
Mode?
YES
Issue UNLOCK BYPASS
RESET Command
PROGRAMMING
COMPLETE
GO TO ERROR
RECOVERY PROCEDURE
Figure 6. Normal and Unlock Bypass Programming Procedures
18
r1.3/May 02