HDMP-1012 Datasheet, PDF (38/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

V_EE
PIN 1
CAP0B
D1
C2
CAP0A
CAP1A
CAP1B
HGND
HGND
TOP VIEW
Tx
GND
GND
V_EE
V_EE
GND
R1
V_EE ^C1
V_EE
R1
C1
V_EE
V_EE
GND
GND
GND
GND
V_EE
V_EE
R1
V_EE ^C1
V_EE
V_EE
R2
PIN 1
CAP0B
D1
C2
CAP0A
CAP1A
CAP1B
GND
GND
GND
V_EE
V_EE
R1
V_EE ^C1
TOP VIEW
ECLGND
HGND
ECLGND
Rx
R2
V_EE
R1
C1
V_EE
V_EE
GND
GND
GND
GND
V_EE
V_EE
R1
V_EE ^C1
R2
V_EE
R1 = V_EE BYPASS DAMPING RESISTOR
R2 = ECLGND DAMPING RESISTOR
C1 = V_EE BYPASS CAPACITOR
C2 = PLL INTEGRATOR CAPACITOR
D1 = OPTIONAL CLAMPING DIODE
10 OHMS
10 OHMS
0.1 µF
0.1 µF
Figure 20. Power Supply Bypass.
610
ground plane, assuming that it is
a fairly clean ground plane. Thus,
all of the separate grounds
(HGND, GND, and ECLGND) can
be connected onto this plane. The
bypassing of VEE to ground
should be accomplished with a
capacitor (C1) of 0.1 µF and a
series resistor (R1) of 10 Ω. This
series RC network prevents
possible oscillations caused by
package, capacitor, and layout
parasitics. The Rx ECLGND leads
are grounded using R2. These 10
Ω resistors reduce excessive
ringing caused by current spikes
generated by the parasitic
inductance in the ECLGND leads.
This effect is more pronounced in
the receiver because of its
multiple ECL outputs.The
ECLGND pins of the Tx are
simply grounded.
In some instances, if the VCO of
either the Tx or the Rx are at the
extreme high end, the frequency
of STRBOUT exceeds the
maximum frequency allowed by
the hosts. In this case, it is
recommended that a diode clamp,
D1, be used across the integrating
cap C2, such that the upper
frequency is limited. The typical
swing of C2 is ± 0.8 volts, and
thus, the clamping diode should
have a turn-on voltage below 0.8
V, such as with germanium or
schottky diodes. This will vary
with each application. This diode
will also aid the Tx and Rx in the
initial frequency lock-in process.
Electrical Connections
The electrical I/Os for both the Tx
and Rx are shown in Figures 21-
23. The data sheet uses the
prefix, I and O, on the logic type
in order to identify input and
output lines respectively.
Additional information on pin
names and their functions can be