HDMP-1012 Datasheet, PDF (37/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

the flag input to signify the two
frames. The setup and hold times
are referenced to 1/2 frame
period of D0-D19, or 90 deg,
from the edges of STRBIN. The
multiplexer delay, t_mux, should be
considered for timing margins.
The STRBOUT is derived from the
internal sampling clock, and thus
has a frequency double that of
STRBIN. The falling edge of
STRBOUT appears after the rising
and falling edges of STRBIN after
a delay of T_strb. Other interlacing
techniques can also be achieved
with edge-triggered latches for
improved timing margins.
In the Rx side, the frame D0-D19
are demultiplexed back to the
original C0-C19, and C20-C39
frames with the use of external
edge-triggered flip-flops. The
toggle clock of the flip-flops,
RCLK, is derived by the state of
the FLAG bit. RCLK toggle with
the rising edge of STRBOUT with
a delay of t_da. The two frames
appear with the rising and falling
edges of RCLK with a delay of t_db.
All of the synchronous outputs
and state machine outputs appear
after the falling edge of STRBOUT
with delays of t_d1 and t_d2
respectively.
The lower frame of C0-C19 can
be delayed further with additional
latches so that both C0-C19 and
C20-C39 frames are synchronous.
Supply Bypassing and
Integrator Capacitor
Figure 20 shows the location of
the PLL integrator capacitors,
power supply capacitors and
required grounding for the Tx and
Rx chips.
Integrating Capacitor
The integrating capacitors (C2)
are required by both the Tx and
Rx to function properly. These
caps are used by the PLL for
frequency and phase lock and
directly set the stability and
lockup times. The designed value
of C2 is 0.1 µF, with a tolerance
of ± 10%. The internal charging
currents are scaled with the DIV0
and DIV1 settings such that the
same capacitor value works with
all four frequency bands. Larger
values of C2 improve jitter
performance, but extend the
lockup times.
Power Supply Bypassing and
Grounding
The G-LINK chip set has been
tested to work well with a single
CAV*, DAV*
C00 - C19
C20 - C39
STRBOUT
0 D00 - D19
2:1
MUX FLAG
1
STRBIN
PLL
Tx
CONFIGURATIONS
Rx
CONFIGURATIONS
D00 - D19
FLAG
CAV*, DAV*, FF
LINKRDY,
ERROR
C00 - C19
C20 - C39
RCLK
STRBOUT
STAT0
STAT1
STRBIN
FLAG
1/2 FRAME
PERIOD
1/2 FRAME
PERIOD
CAV*, DAV*
C00 - C19
C20 - C39
D00 - D19
t_s
t_h
t_strb
C00 - C19
t_s
t_h
t_s
t_h
t_mux
C20 - C39
t_s
t_h
STRBOUT
CAV*, DAV*
FF, LINKRDY
ERROR
D00 - D19
t_d1
t_d2
C00 - C19
C20 - C39
FLAG
RCLK
C00 - C19
t_da
t_db
t_da
t_db
STRBOUT
C20 - C39
t_s = SETUP TIME
t_h = HOLD TIME
t_strb = STRBIN TO STRBOUT DELAY
t_mux = 2:1 MULTIPLEXER DELAY
STAT0
STAT1
t_d1 = STRBOUT TO SYNCHRONOUS OUTPUTS DELAY
t_d2 = STRBOUT TO STATE MACHINE OUTPUTS DELAY
t_da = STRBOUT TO RCLK DELAY
t_db = RCLK TO C00-C39 OUTPUT DELAY
Figure 19. Transmitter and Receiver Data Interface and Timing for Double Frame Mode (MDFSEL=0).
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