HDMP-1012 Datasheet, PDF (16/42 Pages) Agilent(Hewlett-Packard) – 4Low Cost Gigabit Rate Transmit/Receive Chip Set

Tx I/O Definition (cont’d.)
Name Pin Type
Signal
EHCLKSEL 78 I-ECL EHCLK Enable: When active, this input causes the STRBIN inputs
to be used for the transmit serial clock, rather than the internal VCO
clock. This is useful for generating extremely low jitter test signals, or
for operating the link at speeds that are not within the VCO range.
When the STRBIN is active, it is necessary for the data source to take
its clock from the link rather than the usual operation where the Link
phase-locks onto the data source clock.
FF
68 I-ECL Fill Frame Select: When neither CAV or DAV is asserted, or when
ED is false, fill frames are automatically transmitted to allow the Rx
chip to maintain lock. The type of fill frame sent is determined by
the state of this pin. FF0s are sent if low, and either FF1a or FF1b is
sent if FF is high. The choice of FF1a and FF1b is determined by the
state of the cumulative line DC balance.
FLAG
60 I-ECL Extra Flag Bit: When FLAGSEL is active, this input is sent as an
extra data bit in addition to the normal Data inputs. When FLAGSEL
is not asserted, this input is ignored and the transmitted Flag bit is
internally alternated to allow the Rx chip to perform enhanced frame
error detection.
FLAGSEL
71 I-ECL Flag Bit Mode Select: When this input is high, the extra FLAG bit
input is sent as an extra transparent data bit. Otherwise, the FLAG
input is ignored and the transmitted flag bit is internally alternated
by the transmitter. The Rx chip can provide enhanced frame error
detection by checking for strict alternation of the flag bit during data
frames. The FLAGSEL input on the Rx chip should be set to the same
value as the Tx FLAGSEL input.
GND
23
S Ground: Normally 0 volts. This ground is used for everything other
24
than the noisy ECL outputs.
43
44
52
63
64
72
79
HCLK
HCLK*
11 O-BLL High Speed Clock Monitor: Used to monitor actual clock signal
12
used to transmit the serial data. This signal will either be the divided
VCO output, or the divided EHCLK external clock input, depending
on the value of the EHCLKSEL input.
HCLKON
10 I-ECL HCLK Power-down Control: When this pin is de-asserted, the
HCLK, HCLK* outputs are powered down to reduce power
dissipation.
HGND
7
S High Speed Ground: Normally 0 volts. This ground is used to
13
provide a clean reference for STRBIN and STRBIN* inputs. For
optimum impedance matching, it is suggested that the physical
distance between this pin and the ground plane be minimized.
588